(1) Field of the Invention
The present invention relates to semiconductor processing for integrated circuits, and more particularly relates to a method for accurately measuring layer-to-layer overlay alignment using improved overlay targets on the substrate and a novel overlay alignment algorithm.
(2) Description of the Prior Art
Semiconductor processing for forming integrated circuits requires a series of processing steps. These processing steps include the deposition and patterning of material layers such as insulating layers, polysilicon layers, and metal layers. The material layers are typically patterned using a photoresist layer that is patterned over the material layer using a photomask or reticle. Typically the photomask has alignment marks or keys that are aligned to alignment marks formed in the previous layer on the substrate. However, as the integrated circuit feature sizes continue to decrease to provide increasing circuit density, it becomes increasingly difficult to measure the alignment accuracy of one masking level to the previous level. This overlay metrology problem becomes particularly difficult at submicrometer feature sizes where overlay alignment tolerances are reduced to provide reliable semiconductor devices.
This overlay metrology problem is further exacerbated by the asymmetries in the profile of the material layer over the alignment mark on the substrate. This asymmetry results in distortion of the detection signal used by the software algorithm to align the mask to the alignment mark by the photoresist exposure tool on the substrate, such as in a step-and-repeat exposure system. Also, this asymmetry in the material layer over the overlay target makes it more difficult to provide an accurate overlay metrology.
These asymmetries in the layer can result from asymmetric depositions and/or chemical/mechanical polishing. For example, the chemical/mechanical polishing is used to planarize the layer, and provides a shallow depth of focus (DOF), which are required for optically exposing distortion-free high-resolution photolithographic images. Also, the planar surface allows patterning of the next material layer using directional etching (anisotropic plasma etching) without leaving residue in recesses in the underlying layer.
To better appreciate the metrology alignment problem, top views of some prior-art overlay targets metrologies are depicted in FIGS. 1A and 2. In FIG. 1A, a typical Box-in-Box overlay target 1 is shown, for example by forming a recessed area in a material layer 10 on the substrate, as depicted in the cross section in FIG. 1B. Ideally, a corresponding smaller box 2 on the photomask or reticle is aligned to the larger box 1 so that the centers C.sub.0 of the large and small boxes are aligned. However, when an asymmetric layer 12 is formed over the overlay target 1, the edge detection signal S from the edge of the overlay target 1 is shifted to S' resulting in a misalignment of D, as shown in FIG. 1C for a scan across the overlay target.
FIG. 1C shows the cross section 1B-1B' of FIG. 1A. This also results in misalignment of the center of the box from C.sub.0 to C.sub.0 ' as depicted in FIGS. 1A-1C. The misalignment along 1B-1B' between the centers can be expressed as D=(C.sub.0 -C.sub.0 ') and results from an error in the edge detection signal that is provided to the software algorithm for measuring the alignment. FIG. 2 shows an alternative Bar-in-Bar overlay target where the overlay target alignment bars 4 on the photomask or the etched image in layer 12 are aligned to the overlay target alignment bars 3 etched in layer 10 on the substrate. This alignment measurement is also susceptible to edge detection error similar to the Box-in-Box alignment metrology.
FIG. 3 shows a typical reticle 5 used in a step-and-repeat tool to expose and pattern the photoresist layer in area 14 to form the integrated circuits for each chip. The reticle (or mask) 5 is then stepped across the substrate (wafer) to fabricate an array of integrated circuits on the substrate. The alignment mark 2 on the reticle 5, such as the Box-on-Box alignment mark, is aligned to the alignment mark 1 in a kerf area 6 on the substrate along the perimeter of the reticle 5. The alignment algorithm is then used to align the alignment mark 2 to the alignment mark 1 in layer 10 on the substrate. Unfortunately, if the underlying layer 10 is asymmetric over the alignment mark 1, then misalignment can occur, and therefore it is desirable to have an overlay metrology that can more accurately measure this alignment error.
Several methods of improving the measurement and alignment metrologies have been reported. Chung et al. in U.S. Pat. No. 5,633,505 teach a method for checking the overlay alignment for the global alignment, in which subsequent masks are aligned to global alignment marks on the periphery of the substrate. Another method by Bae in U.S. Pat. No. 5,498,500 teaches a method for utilizing the overlay alignment marks to determine the overlay error for multilevels of patterns, and Turner et al. in U.S. Pat. No. 5,365,072 describe a variety of alignment marks for positioning a substrate under a microscope. Conway et al. in U.S. Pat. No. 5,087,537 describe a method using a repetitive pattern of relatively large elements such as rectangles oriented in orthogonal and angular fashion. And a second series of fine lines of varying widths are formed at the next photoresist level over the first pattern. The patterns can then be examined in a scanning electron microscope for alignment and image size. This method is particularly useful for methods of exposing the photoresist that do not use exposure masks, such as electron beam exposure tools.
There is still a need in the semiconductor industry for improved overlay target metrology using novel overlay targets and an algorithm that measures overlay with more accuracy. This includes the need to minimize edge detection errors that can result from a material layer having an asymmetric profile over the overlay target.